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sm5846ap seiko npc corporation ? multi-function digital filter overview the sm5846ap is a multi-function digital ?ter that incorporates 4/8 times oversampling digital audio signal reproduction, digital deemphasis, digital attenuation and soft mute functions. the i/o interface allows serial data transmission of 16/20/24/32-bit input data and 20/24-bit output data. features functions 8-times oversampling (interpolation) switchable 8/4 times oversampling output two master clock frequencies (refer to clock functions) 384fs/512fs (normal-speed sampling) 192fs/256fs (high-speed sampling) digital deemphasis compatible with 32/44.1/48khz (normal- speed) and 64/88.2/96khz (high-speed) input sampling frequencies on/off control digital attenuator 128-step attenuation using linear 7-bit data set- ting soft muting 1016/fs (normal-speed sampling) 2032/fs (high-speed sampling) output data round-off operation (normal round-off or rectangular distribution dither round-off) selectable lr clock polarity microprocessor controllable input data format 2s complement, msb ?st, alternating l/r serial 16/20/24/32-bit data selectable output data format 2s complement, msb ?st, simultaneous l/r serial 20/24-bit data selectable. 24-bit internal data processing jitter-free mode/synchronous mode selectable crystal oscillator circuit built-in ttl-compatible outputs molybdenum-gate cmos filter construction interpolation ?ter (linear 3-stage fir ?ter) normal-speed sampling mode 1st stage (fs to 2fs) 121st order 2nd stage (2fs to 4fs) 21st order 3rd stage (4fs to 8fs) 13th order high-speed sampling mode 1st stage (fs to 2fs) 177th order 2nd stage (2fs to 4fs) 29th order 3rd stage (4fs to 8fs) 17th order deemphasis ?ter (iir ?ter) arithmetic units ?5 24-bit parallel adder 32-bit accumulator over?w limiter built-in applications digital audio equipment ordering infomation device package sm5846ap 28-pin dip
sm5846ap seiko npc corporation ? pinout (top view) package dimensions (unit: mm) lrci bcko wcko dor bcki mds 1 2 3 4 5 6 7 18 19 20 21 22 23 24 dol vdd2 din cken xti xto vdd1 dith cko vss1 cks asel2/mdck 8 9 10 11 12 hs/mdt vss2 asel1 test2 15 16 17 obs test1 13 14 28 27 26 25 sync/mdle rst deem lrs 2.54 0.45 0.1 4.5 0.3 37.3 0.3 13.8 0.2 1.5 + 0.30 ? 0.05 7.7 0.5 3.8 0.1 3.2 0.2 15.2 0 to 15 0.25 + 0.10 ? 0.05
sm5846ap seiko npc corporation ? filter characteristics normal-speed sampling overall frequency characteristic passband frequency characteristic transition band characteristic parameter rating passband bandwidth 0 to 0.4535fs stopband bandwidth 0.5465 to 7.4535fs passband ripple ?.0004db stopband attenuation 75db group delay time 1 1. the time difference due to digital ?ter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs). when cks is high: 63.89/fs (when sync is low) and 63.51/fs to 64.26/fs (when sync is high) when cks is low: 63.76/fs (when sync is low) and 63.59/fs to 64.14/fs (when sync is high) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 frequency [fs] 140 120 100 80 60 40 20 0 attenuation [db] 0.000 0.125 0.250 0.375 0.500 0.0005 0.00025 0.00000 ? 0.00025 ? 0.0005 frequency [fs] attenuation [db] 0.00 0.125 0.25 0.375 0.50 0.625 0.75 0.825 1.00 140 120 100 80 60 40 20 0 frequency [fs] attenuation [db]
sm5846ap seiko npc corporation ? high-speed sampling (8fs output) overall frequency characteristic passband frequency characteristic transition band characteristic parameter rating passband bandwidth 0 to 0.4535fs stopband bandwidth 0.5465 to 7.4535fs passband ripple ?.00001db stopband attenuation 105db group delay time 1 1. the time difference due to digital ?ter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs). when cks is high: 51.91/fs (when sync is low) and 51.53/fs to 52.28/fs (when sync is high) when cks is low: 51.78/fs (when sync is low) and 51.40/fs to 52.15/fs (when sync is high) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 140 120 100 80 60 40 20 0 frequency [fs] attenuation [db] 0.000 0.125 0.250 0.375 0.500 0.0001 0.00005 0.00000 ? 0.00005 ? 0.0001 frequency [fs] attenuation [db] 0.00 0.125 0.25 0.375 0.50 0.625 0.75 0.825 1.00 140 120 100 80 60 40 20 0 frequency [fs] attenuation [db]
sm5846ap seiko npc corporation ? high-speed sampling (4fs output) overall frequency characteristic passband frequency characteristic transition band characteristic parameter rating passband bandwidth 0 to 0.4535fs stopband bandwidth 0.5465 to 7.4535fs passband ripple ?.00001db stopband attenuation 104db group delay time 1 1. the time difference due to digital ?ter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs). when cks is high: 50.78/fs (when sync is low) and 50.40/fs to 51.15/fs (when sync is high) when cks is low: 50.77/fs (when sync is low) and 50.40/fs to 51.15/fs (when sync is high) 140 120 100 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 frequency [fs] attenuation [db] 0.000 0.125 0.250 0.375 0.500 0.0001 0.00005 0.00000 ? 0.00005 ? 0.0001 frequency [fs] attenuation [db] 0.125 0.25 0.375 0.50 0.625 0.75 0.825 1.00 140 120 100 80 60 40 20 0 frequency [fs] attenuation [db]
sm5846ap seiko npc corporation ? deemphasis filter characteristics (normal-speed sampling) deemphasis passband characteristic (logarithmic scale) deemphasis passband characteristic (linear scale) parameter rating sampling frequency (fs) 32khz 44.1khz 48khz passband bandwidth 0 to 14.5khz 0 to 20.0khz 0 to 21.7khz deviation from ideal characteristics attenuation ?.01db phase 0 to 6 the phase traces are from top to bottom fs = 32/44.1/48khz, respectively. the phase traces are from top to bottom fs = 32/44.1/48khz, respectively. frequency [hz] attenuation [db] 0 2 4 6 8 10 0 ? 20 ? 40 ? 60 10 20 50 100 200 500 1k 2k 5k 10k 20k phase attenuation phase [ ] frequency [hz] attenuation [db] 0 2 4 6 8 10 0 ? 20 ? 40 ? 60 0 4k 8k 12k 16k 20k 22k 24k phase attenuation phase [ ]
sm5846ap seiko npc corporation ? deemphasis filter characteristics (high-speed sampling) deemphasis passband characteristic (logarithmic scale) deemphasis passband characteristic (linear scale) parameter rating sampling frequency (fs) 64khz 88.2khz 96khz passband bandwidth 0 to 29.0khz 0 to 40.0khz 0 to 43.5khz deviation from ideal characteristics attenuation ?.001db phase 0 to 1 the phase traces are from top to bottom fs = 64/88.2/96khz, respectively. the phase traces are from top to bottom fs = 64/88.2/96khz, respectively. attenuation [db] 0 2 4 6 8 10 0 ? 20 ? 40 ? 60 phase [ ] frequency [hz] 10 20 50 100 200 500 1k 2k 5k 10k 20k phase attenuation frequency [hz] attenuation [db] 0 2 4 6 8 10 0 ? 20 ? 40 ? 60 0 4k 8k 12k 16k 20k 22k 24k phase [ ] phase attenuation
sm5846ap seiko npc corporation ? specifications absolute maximum ratings v ss = 0v recommended operating conditions v ss = 0v dc electrical characteristics v dd = 4.5 to 5.5v, v ss = 0v, ta = ? 20 to 70 c parameter symbol rating unit supply voltage range v dd ? 0.3 to 7.0 v input voltage range v in ? 0.3 to v dd + 0.3 v storage temperature range t stg ? 40 to 125 c power dissipation p d 750 mw parameter symbol rating unit supply voltage range v dd 4.5 to 5.5 v operating temperature range t opr ? 20 to 70 c parameter symbol condition rating unit min typ max supply current consumption 1 1. v dd = 5.0v, f sys = 18.432mhz, 384fs operation, no output load. i dd 110 130 ma high-level input voltage v ih all inputs 0.7v dd v low-level input voltage v il all inputs 0.3v dd v xti ac-coupled input voltage v inac 0.3v dd v p-p high-level output voltage v oh all outputs, i oh = ? 1ma v dd ? 0.4 v low-level output voltage v ol all outputs, i ol = 2ma 0.4 v xti high-level input current i ih v in = v dd ?020a xti low-level input current i il v in = v ss ?020a low-level input current i il inputs excluding xti, v in = v ss ?020a input leakage current i lh inputs excluding xti, v in = dv dd 1.0 ?
sm5846ap seiko npc corporation ? ac characteristics xti input timing v dd = 4.5 to 5.5v, v ss = 0v, ta = ? 20 to 70 c rst input timing v dd = 4.5 to 5.5v, v ss = 0v, ta = ? 20 to 70 c parameter symbol condition rating unit min typ max oscillator frequency f osc 10 18.5 mhz xti clock pulse cycle time t xi 54 ns xti high-level clock pulsewidth t cwh 24 ns xti low-level clock pulsewidth t cwl 24 ns parameter symbol condition rating unit min typ max reset pulsewidth t rst when power is applied 1 ? at all other times 50 ns t xi t chw t chw xti 0.5v dd rst t rst 0.5v dd
sm5846ap seiko npc corporation ?0 serial data input timing (bcki, din, lrci) v dd = 4.5 to 5.5v, v ss = 0v, ta = ? 20 to 70 c parameter symbol condition rating unit min typ max bcki pulse cycle time t bcy 100 ns bcki high-level pulsewidth t bcwh 50 ns bcki low-level pulsewidth t bcwl 50 ns din setup time t ds 20 ns din hold time t dh 20 ns bcki rising edge to lrci edge time t bl 50 ns lrci edge to bcki rising edge time t lb 50 ns lrci 0.5v dd bcki t bcy t bcwh t bcwl t ds t dh t bl t lb din 0.5v dd 0.5v dd valid
sm5846ap seiko npc corporation ?1 microprocessor serial interface timing (mdck, mdt, mdle) v dd = 4.5 to 5.5v, v ss = 0v, ta = ? 20 to 70 c parameter symbol condition rating unit min typ max mdck pulse cycle time t mcy 100 ns mdck high-level pulsewidth t mcwh 50 ns mdck low-level pulsewidth t mcwl 50 ns mdt setup time t mds 20 ns mdt hold time t mdh 20 ns mdck rising edge to mdle edge time t mcl 50 ns mdle edge to mdck rising edge time t mlc 50 ns mdle high-level pulsewidth t mlwh 20 ns mdle low-level pulsewidth t mlwl 20 ns 0.5v dd mdt 0.5v dd mdle 0.5v dd mdck t mcy t mcwh t mcwl t mds t mdh t mcl t mcl t mlwl t mlwh
sm5846ap seiko npc corporation ?2 output signal timing (cko, bcko, dor, dol, wcko) v dd = 4.5 to 5.5v, v ss = 0v, ta = ? 20 to 70 c, c l = 15pf cko output bcko output dor, dol, wcko output parameter symbol condition rating unit min typ max xti to cko propagation delay time t ckh ?735 ns t ckl ?735 xti to bcko propagation delay time t sbh normal and high-speed mode 4fs output ?060 ns t sbl ?060 t sbh high-speed mode 8fs output ?060 t sbl ?060 bcko to dor propagation delay time t bdh ? 515 ns t bdl ? 515 bcko to dol propagation delay time t bdh ? 515 ns t bdl ? 515 bcko to wcko propagation delay time t bdh ? 515 ns t bdl ? 515 *1 : high speed mode 8fs output *2 : normal and high-speed mode 8fs output xti t ckh cko t ckl 0.5v dd 1.5v xti 0.5v dd 1.5v 1.5v t sbl t sbl bcko * 1 t sbh t sbh bcko * 2 bcko dor dol wcko t bdh t bdl 1.5v 1.5v
sm5846ap seiko npc corporation ?3 pin description number name i/o 1 1. ip = input pin with pull-up resistor, i = input, o = output description 1 din ip data input 2 bcki ip bit clock input 3 vdd1 5v supply voltage 4 dith ip dither on/off control 5 cken ip crystal oscillator operation enable 6 xti i crystal oscillator input/external clock input 7 xto o crystal oscillator output 8 vss1 ground 9 cko o master clock output 10 cks ip master clock input frequency select 11 asel2/mdck ip operating mode select/microprocessor interface clock input 12 hs /mdt ip operating mode select/microprocessor interface data input 13 sync/mdle ip sync mode select/microprocessor interface latch enable input 14 rst ip reset input 15 lrs ip lr clock polarity select 16 deem ip deemphasis on/off select 17 test1 ip test pin 1. tie high or leave open for normal operation. 18 test2 ip test pin 2. tie low for normal operation. 19 obs ip output data length select 20 asel1 ip operating mode select 21 vss2 ground 22 vdd2 5v supply voltage 23 dor o right-channel data output 24 dol o left-channel data output 25 wcko o word clock output 26 bcko o output data bit clock output 27 mds ip mode set method select 28 lrci ip lr clock input
sm5846ap seiko npc corporation ?4 block diagram xto xti cko cken cks output data interface (serial input) control rst vss2 clock generator reset circuit mds hs/mdt asel2/mdck asel1 wcko obs dith vdd2 vdd1 vss1 control control output data interface (serial output) operation mode control micro controller interface (serial input) arithmetic block deem test2 test1 sync/mdle lrs lrci bcki din bcko dol dor
sm5846ap seiko npc corporation ?5 system configuration data flow att1/att2 soft muting uses the d-att function to set the gain to ? . normal-speed sampling (fs = 32/44.1/48khz) high-speed sampling (fs = 64/88.2/96khz) dsp din bcki lrci cko cken xti xto cks vss1 vss2 vdd1 wcko bcko dol dor test1 test2 obs lrs dith deen sync/mle asel2/mck asel1 hs/mdt mds +5v dac reset circuits oscilation control rst vdd2 +5v +5v setting setting in (fs) firi 2fs 2fs 2fs 2fs 4fs demi dly att1 fir2 fir3 fs 2fs 2fs 2fs 2fs 4fs 8fs swa (121 order) 8fs (d-att / soft mute) out lpf lpf ( 2) ( 2) lpf ( 2) (8fs) (21 order) (13 order) in (fs) fir4 2fs fs 2fs 8fs swb(177 order) 4fs 4fs lpf 4fs fir5 4fs (29 order) dem2 4fs swd(on / off) att2 (d-att / soft mute) 4fs 4fs (17 order) fir6 8fs ( 8fs / 4fs ) out 8fs/4fs swg ( 8fs / 4fs ) ( 2) lpf ( 2) lpf ( 2)
sm5846ap seiko npc corporation ?6 functional description mode switching and function switching the sm5846ap supports several operating modes and function switches. internal control ags, set by the dig- ital inputs or serial data input signal from a microprocessor, determine the status of those function switches. mode switching/function switch controls control request switching mds input and device control mode switching/function switching is performed under input pin control when mds is high, and under internal ag control when mds is low. input pin functions when mds is low all pins that are part of the microprocessor interface can be used whenever mds is low. stage name control request function input control ?g system mds yes ic control request switch (input pin/control ?g) operating mode switch hs ye s ye s operating mode switching asel2 yes yes asel1 yes yes clock switch cks yes input clock frequency switching cken yes crystal oscillator operating control switching filter switch deem yes yes deemphasis on/off switching fsel2 yes deemphasis ?ter sampling frequency set fsel1 yes mute yes mute on/off control dith ye s (pos. logic) ye s (neg. logic) dither on/off control input interface switch sync yes yes jitter-free/sync mode switching lrs yes lrci (lr clock) input polarity switching ibs2 yes input data length set ibs1 yes output interface switch obs yes yes output data length set mds 1 1. switching mds during device operation is prohibited. control request high input pins low control ?gs pin name function notes hs /mdt serial data transfer data clock used for the microprocessor interface asel2/mdck serial data transfer clock input sync/mdle serial data transfer latch enable input cks cks function switch input input pin control only because there is no corresponding control ?g. cken cken function switch input lrs lrs function switch input
sm5846ap seiko npc corporation ?7 control ?g functions when msd is high (default) other requests are controlled by internal ag only because there is no corresponding input pin. these control ags are valid when mds is high. the default values are shown in the following table. clock functions input clock frequency switching (cks) this switch is used to select the input clock frequency 384fs or 512fs (normal-speed sampling), and 192fs or 256fs (high-speed sampling). crystal oscillator control switch (cken) this switch is used to start/stop the crystal oscillator circuit. flag name default value default setting fsel2 high 44.1khz deemphasis ?ter sampling frequency fsel1 high mute high muting off ibs2 low 16-bit input data length ibs1 high cks input sampling frequency fs [khz] system clock notes frequency [mhz] [ fs] low 32 16.384 512fs normal-speed sampling mode 64 16.384 256fs high-speed sampling mode high 32 12.288 384fs normal-speed sampling mode 44.1 16.9344 48 18.432 64 12.288 192fs high-speed sampling mode 88.2 16.9344 96 18.432 cken crystal oscillator operation high oscillating low stopped
sm5846ap seiko npc corporation ?8 crystal oscillator circuit the built-in crystal oscillator circuit comprises a feedback resistor and several logic gates. the system clock can be generated using an external quartz crystal and 2 capacitors. external clock when an external clock is used, xto is left open-circuit and the clock signal is input on xti. system clock cko system clock output xto xti cken oscilation/stop contorol rf x'tal c1 c2 system clock cko system clock output xti cken oscilation/ stop contorol rf open external clock input xto
sm5846ap seiko npc corporation ?9 other control settings input data length select isb1 and isb2 ags are used to set the input data length. lrci input polarity select pin lrs is used to set the lrci input polarity. sync mode select the sync pin or ag setting can be used to select either jitter-free mode or sync mode to control syn- chronization between input data and internal arith- metic blocks. filter stage operating mode the sm5846a supports 3 different operating modes to control output data rate switching. the operating mode is selected by the state of hs , asel1 and asel2. operating speed and sampling frequency the sm5846ap supports sampling frequencies of 32/44.1/48khz (normal-speed sampling mode) and 64/88.2/96khz (high-speed sampling mode). deemphasis ?ter the sm5846ap contains a digital deemphasis lter controlled by deem. the sampling frequency is selected by fsel1 and fsel2. digital attenuator the digital attenuator is controlled by serial data from the microprocessor interface. this data can set attenuation and muting. note that the digital attenua- tor is only enabled when mds is low. att1 and att2 are used to set the attenuation in normal-speed sampling and high-speed sampling, respectively. ibs2 ibs1 input data length notes high high 20 bits the length is set to the default value of 16 bits (ibs2 = low and ibs1 = high) after a reset. high low 24 bits low high 16 bits low low 32 bits lrs lrci input channel high high left high low right low high right low low left sync mode notes high jitter-free mode the sync ?g is set high (default) after a reset. low sync mode hs asel1 asel2 operating mode 1 1. only the above 3 modes are valid. speed oversampling high low high normal-speed sampling 8-times low high high high-speed sampling 8-times low 4-times operating speed input sampling frequency normal-speed sampling 32/44.1/48khz high-speed sampling 64/88.2/96khz deem deemphasis high on low off fsel2 fsel1 sampling frequency fs [khz] normal-speed sampling high-speed sampling high high 44.1 88.2 high low 48 96 low high 44.1 88.2 low low 32 64
sm5846ap seiko npc corporation ?0 attenuation setting the data stored in the d-att attenuation register, accessed through the microprocessor interface, determines the attenuation setting of the digital attenuator. the d-att register data format is shown below. the attenuation setting is given by the following equations. the attenuation for a selection of values is given in the following table. digital attenuator operation the attenuation register is reset to 0 (attenuation = 0 db) after a system reset signal. when data is written to the attenuation register, through the microprocessor interface, the attenuation changes from the current value to the new value at the speed shown in the following table. soft muting operation soft muting on/off is controlled by the mute ag, accessed through the microprocessor interface. when muting is on, the attenuation ramps down to ? at the speed shown in the table. similarly when muting is off, the attenuation level returns to the original value at the same speed. if the contents of the datt attenuation register are changed while muting is on (attenuation = ? ), only the register contents are replaced. if muting is subsequently turned off, the attenuation value changes to the new value at the same speed as shown in the table. datt register value microprocess or command [hex] attenuation [db] relative gain 0 00h 0 1.0 1 01h ? 0.137 0.984375 2 02h ? 0.206 0.9765625 63 3fh ? 6.021 0.5 64 40h ? 6.157 0.4921875 125 7dh ? 36.12 0.015625 126 7eh ? 42.14 0.0078125 127 7fh ? 0 "0"a1a2a3a4a5a6a7 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 msb lsb register information datt attenation data (7bit) attenuation = 0 [db] (datt = 0) (datt = 127) (0 < datt < 127) attenuation = 20log 10 attenuation = ? [db] 128 127 ? datt operating speed speed of attenuation change time from min. to max. attenuation normal-speed sampling 8/fs per step change 1016/fs (23.0ms at 44.1khz) high-speed sampling 16/fs per step change 2032/fs (23.0ms at 88.2khz) mute muting notes high off the mute ?g is set high (default) after a system reset. low on
sm5846ap seiko npc corporation ?1 output data round-off output data round-off processing is required because the internal data length of the digital lter is different from the output data length (internal data processing width > output data width). the sm5846ap can select either normal round-off or dither round-off on the output data. round-off processing can be selected either by input pin or con- trol ag settings. normal round-off normal round-off is carried out by adding 1/2 lsb to the lter output data to form 20/24-bit output data, depending on the selected output data length. dither round-off dither round-off is carried out by adding a pseudo- random number between 0 and 1 lsb, derived from a rectangular distribution, to the lter output data to form 20/24-bit output data, depending on the selected output data length. the random number rectangular distribution is shown below (average = 1/2 lsb). over?w limiter if an over ow or under ow condition occurs after round-off or lter arithmetic processing, the output data will be xed at positive or negative maximum value. mds dith pin dith ?g output data round-off notes high high dither round-off the dith ?g is set high (default) after a system reset. low normal round-off low high normal round-off low dither round-off probavility 0 1/2 1 (lsb)
sm5846ap seiko npc corporation ?2 audio data input interface serial data transmission is used for the digital audio data input. the data has the following format: 16/20/24/32-bit data length alternating left/right-channel serial data transmis- sion msb rst rear packed 2s complement for negative values audio data input interface pins audio data is input using pins lrci, bcki, and din. the lrci input polarity is determined by pin lrs. serial data on din is input to the serial-to-parallel shift register on the falling edge of the bit transfer clock bcki. the parallel data is then stored in the left/right-channel input buffers on the high/low- level pulse of the lrci latch clock signal, depending on the selected polarity of the lrci clock. audio data input interface schematic pin name function lrci left/right-channel latch clock input bcki bit transfer clock input din serial data input lrs lrci input polarity switch 32bit sipo shiftregister 32bit register left channel input data buffer right channel input data buffer right channel input data left channel input data 32bit register din bcki d q d q d q lrci lrs c c c
sm5846ap seiko npc corporation ?3 input data interface example (lrs = high) 32-bit input data length 24-bit input data length 20-bit input data length 16-bit input data length fs 31 din bcki (64fs) left channel input data lrci (msb) (lsb) (msb) (lsb) 30 29 28 2 1 0 31 30 29 28 2 0 1 right channel input data fs din bcki (64fs) lrci (msb) (lsb) (msb) (lsb) 23 22 2 1 0 23 22 2 0 1 left channel input data right channel input data fs din bcki (64fs) lrci (msb) (lsb) (msb) (lsb) 19 18 2 1 0 19 18 2 0 1 right channel input data left channel input data fs din bcki (64fs) lrci (msb) (lsb) (msb) (lsb) 15 14 1 0 15 14 1 0 left channel input data right channel input data
sm5846ap seiko npc corporation ?4 input data validity 32-bit input data length 24-bit input data length 20-bit input data length 16-bit input data length 31 30 28 26 24 8 6 4 2 0 polarity mark decimal point effective number of bits (24bits) input data (32bits) low order 8 bits cut it off (no round-offattention) 23 22 20 18 16 6 4 2 0 polarity mark decimal point effective number of bits (24bits) input data (24bits) 19 18 16 14 4 2 0 0 0 0 0 decimal point effective number of bits (24bits) input data (20bits) polarity mark input to "0"(4 bits) 15 14 12 2 0 0 0 0 0 0 0 0 0 0 polarity mark effective number of bits (24bits) input data (16bits) input to "0"(8 bits) decimal point
sm5846ap seiko npc corporation ?5 audio data output interface serial data transmission is used for the digital audio data output. the data has the following format: 20/24-bit data length simultaneous left/right-channel serial data trans- mission msb rst bit transfer clock burst (npc format) 2s complement for negative values audio data output interface pins audio data is output using pins wcko, bcko, dol and din. serial data is output on dol and dor on the falling edge of the bit transfer clock bcko. generally, external circuits, such as a serial d/a converter, sam- ple the serial data output on dol and dor on the rising edge of the bit transfer clock signal, and then shift the data into a register. at the completion of one data cycle (20/24-bit selectable) transfer, the word clock wcko goes low with a 50% duty ratio. then the external circuit writes parallel data to a buffer register on the falling edge of word clock wcko. output data length select the output data length is set by either the obs pin or ag. pin name function wcko word clock output bcko bit transfer clock output dol left-channel serial data output dor right-channel serial data output obs output data length notes high 24 bits the obs ?g is set low (default) after a system reset. low 20 bits
sm5846ap seiko npc corporation ?6 audio data output interface output data format 24-bit output data length 20-bit output data length l-ch serial dac r-ch serial dac d c stb d d c d dac dol vo vout(l-ch) dor bcko wcko stb in vo vout(r-ch) following block 20/24bit sipo shiftregister 20/24bit sipo shiftregister c 23 22 20 18 16 6 4 2 0 polarity mark decimal point output data (24bits) 19 18 16 14 4 2 0 polarity mark decimal point output data (20bits)
sm5846ap seiko npc corporation ?7 audio data output timing normal-speed sampling: 384fs clock, 24-bit data output, 8fs output data rate normal-speed sampling: 384fs clock, 20-bit data output, 8fs output data rate 1 frame (1/8fs) 11012 24 20 21 22 23 20 2 310 lsb msb f ck /2 (192fs) wcko dol bcko dor 24bits 212 24 18 19 17 10 lsb msb f ck /2 (192fs) wcko dol bcko dor 1 10 20 21 20bits 1 frame (1/8fs)
sm5846ap seiko npc corporation ?8 normal-speed sampling: 512fs clock, 24-bit data output, 8fs output data rate normal-speed sampling: 512fs clock, 20-bit data output, 8fs output data rate 21416 32 25 22 23 21 0 lsb msb f ck /2 (256fs) wcko dol bcko dor 113 15 17 30 18 1 frame (1/8fs) 24bits 21416 32 21 18 19 17 0 lsb msb f ck /2 (256fs) wcko dol bcko dor 113 15 17 30 18 19 20 1 frame (1/8fs) 20bits
sm5846ap seiko npc corporation ?9 high-speed sampling: 192fs clock, 24-bit data output, 8fs output data rate high-speed sampling: 192fs clock, 20-bit data output, 8fs output data rate 21012 24 22 23 21 0 lsb msb f ck (192fs) wcko dol bcko dor 1 20 21 20 321 1 frame (1/8fs) 24bits 21012 24 18 17 0 lsb msb f ck (192fs) wcko dol bcko dor 1 20 21 1 19 1 frame (1/8fs) 20bits
sm5846ap seiko npc corporation ?0 high-speed sampling: 256fs clock, 24-bit data output, 8fs output data rate high-speed sampling: 256fs clock, 20-bit data output, 8fs output data rate 21314 22 21 0 lsb f ck (256fs) wcko dol bcko dor 1 23 msb 15 16 17 18 25 30 32 1 frame (1/8fs) 24bits 21314 18 17 0 lsb f ck (256fs) wcko dol bcko dor 1 19 msb 15 16 17 18 19 20 21 30 32 1 frame (1/8fs) 20bits
sm5846ap seiko npc corporation ?1 high-speed sampling: 192fs clock, 24-bit data output, 4fs output data rate high-speed sampling: 192fs clock, 20-bit data output, 4fs output data rate 10 22 21 3 lsb f ck /2 (96fs) wcko dol bcko dor 1 23 msb 12 20 24 20 210 1 frame (1/4fs) 24bits 10 19 18 lsb f ck /2 (96fs) wcko dol bcko dor 1 msb 12 20 24 17 1 0 21 1 frame (1/4fs) 20bits
sm5846ap seiko npc corporation ?2 high-speed sampling: 256fs clock, 24-bit data output, 4fs output data rate high-speed sampling: 256fs clock, 20-bit data output, 4fs output data rate 14 23 22 lsb f ck /2 (128fs) wcko dol bcko dor 1 msb 25 32 21 0 2 13 15 16 17 18 30 1 frame (1/4fs) 24bits 14 19 18 lsb f ck /2 (128fs) wcko dol bcko dor 1 msb 32 17 0 2 13 15 16 17 18 30 19 20 21 1 frame (1/4fs) 20bits
sm5846ap seiko npc corporation ?3 microprocessor interface microprocessor interface pins when mds is low, the sm5846ap is controlled by internal ags set by serial data transferred over the micro- processor interface comprising mdle, mdck and mdt. internal control ag serial data on mdt is input into an internal shift register on the rising edge of mdck. after 8-bit data has been input, the data in the shift register is stored in one of four internal ag registers on the rising edge of mdle latch enable. the address of the ag register is derived by decoding bits 1 to 3 of the 8-bit data. microprocessor interface microprocessor interface data input timing mdck and mdle can also follow the dotted lines above pin name function mdle microprocessor data latch enable input mdck microprocessor data transfer clock input mdt serial data input mode flag 1 d-att attenation mdt mdck d q 8bit sipo shift register 8bit register 8bit register 8bit register q 8bit register q d q q d q d q d mode flag 2 mode flag 3 decoder mdle c c c c c bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 mdle mdck mdt msb lsb
sm5846ap seiko npc corporation ?4 serial data format address information is displayed in double-line cells of the table. test bits (mode ?g 1 bit 4 and mode ?g 3 bit 6) should be set to 0. system reset when a reset is necessary the device must be reset under the following condi- tions. when power is rst applied when the lrci clock or system clock stop reset input conditions the rst input is active low. at power-on reset, rst must go low and then go high after the xti and lrci clocks stabilize (reset release). reset timing the internal arithmetic registers and output sequence are initialized on the rising edge of the lrci clock after reset release. the internal control ags and d- att attenuation register are initialized after rst goes low. outputs dol and dor are tied low while rst is low. power-on reset using a capacitor the rst input con guration is a schmitt-trigger input with a pull-up resistor, which means that a sim- ple power-on reset circuit can be made by connect- ing a capacitor between rst and vss as shown below. a 0.01f external capacitor is recommended. how- ever, the time constant can be lengthened if longer time is required for the xti and lrci clocks to sta- bilize after power-on. the external capacitor discharges through the inter- nal pull-up resistor at power-off as this is the only possible discharge path. this could cause reset fail- ure if power is reapplied while the external capacitor is discharging. therefore, a diode should be con- nected between rst and vdd to quickly discharge the capacitor and ensure correct power-on reset operation. external power-on reset circuit register bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 d-att attenuation 0 a1 a2 a3 a4 a5 a6 a7 mode ?g 1 1 0 sync test1 = 0 hs fsel1 fsel2 deem mode ?g 2 1 1 mute dith obs ibs1 ibs2 1 mode ?g 3 1 1 asel1 asel2 1 test2 = 0 1 0 internal pull-up register c external capacitor schmitt buffer rst c rst discharge for diode internal pull-up register schmitt buffer external capacitor
sm5846ap seiko npc corporation ?5 internal control ?g/d-att attenuator register initial values when external muting is required the sm5846ap has a relatively long group delay time because multi-stage lters are employed to achieve the desired lter characteristics. under the following conditions, undesirable noise output can occur during the group delay time period. in this case, it may be necessary to use external muting. when power is rst applied. the state of internal registers may be unde ned during power-on. when switching the operating mode. when switching the operating mode using hs, asel1 and asel2, the internal register assign- ments may be changed. if the lrci and/or xti clock stop. if a disturbance occurs during an input data cycle, normal lter output may not be achieved. when switching deemphasis on/off. switching the deemphasis lter parameters may cause switching noise output. when switching the sampling frequency (clock frequency). when switching between input/output data for- mats (including lrci clock polarity switching). note that switching mds is inhibited during system operation. test precautions the following conditions should be maintained for normal operation. mds and dith inputs should not be simulta- neously low. test1 (bit 4 of mode ag 1 register) should not be set to 1. test2 (bit 4 of mode ag 3 register) should be set to 0 after system reset (including power-on). mode ag 3 register bit 5 and/or bit 7 should not be set to 0. register bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 d-att attenuation 0 a1 = 0 a2 = 0 a3 = 0 a4 = 0 a5 = 0 a6 = 0 a7 = 0 mode ?g 1 1 0 sync = 1 test1 = 0 hs = 1 fsel1 = 1 fsel2 = 1 deem = 0 mode ?g 2 1 1 mute = 1 dith = 1 obs = 0 ibs1 = 1 ibs2 = 0 1 mode ?g 3 1 1 asel1 = 1 asel2 = 1 1 test2 = 1 1 0
sm5846ap seiko npc corporation ?6 nc9616ce 2006.04 please pay your attention to the following points at time of using the products shown in this document. the products shown in this document (hereinafter ?roducts? are not intended to be used for the apparatus that exerts harmful in?ence on human lives due to the defects, failure or malfunction of the products. customers are requested to obtain prior written agreeme nt for such use from seiko npc corporation (hereinafter ?pc?. customers shall be solely responsible for, and indemnify and hold npc free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. npc reserves the right to change the speci?ations of the products in order to improve the characteristic or reliability thereof. npc makes no claim o r warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. therefore, npc shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in t his document. any descriptions including applications, circuits, and the parameters of the products in this document are for reference to use the products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further te sting or modi?ation. customers are requested not to export or re-export, directly or indirectly, the products to any country or any ent ity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. customers are req uested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. seiko npc corporation 15-6, nihombashi-kabutocho, chuo-ku, tokyo 103-0026, japan telephone: +81-3-6667-6601 facsimile: +81-3-6667-6611 http://www.npc.co.jp/ email: sales @ npc.co.jp

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